DDR Timing Fundas

DDR Timing

This post will speak about the DDR Timings. Before that we will see what is DDR, how its storing the bits.

What is DRAM, How its Storing the Bits?.

1. DRAM is a type of random-access memory that stores each bit  of data in a separate capacitor  within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1.

2. Memory chip is organized internally as a matrix. At the intersection of each row and column we have a small capacitor that is in charge of storing a ”0“ or a ”1“ – the data.
These memory is controlled by the memory controller.

The flow will be like this:
Memory Controller <——-clocks—> Memory Modules

Double Data Rate(DDRAM)

The name indicates Two Data Chunks per clock cycle. Due the speed its classifies as DDR2 and DDR3

In general the DDR will be named as DDRx-yyyy(DDR2-800). Which is indicates x(2) is the technology generation and yyyy(800) is the clock rate. Using this clockrates for single clock pulse, we can calcuate how many bytes is transferred between the memory controller and the memory module.

Example:
DDR2-800 memories have a maximum theoritical transfer rate is 6400M/Bs. (800 * 8). This is done by multiplying the DDR Clock in Mhz by the Eight(1 byte).
This will give us maximum theoritcal rate in MB/s.

DDR Timings:

DDR need to properly configure to work. Once its configured we use the DDR for our transaction. We need to achieve the timings properly for the better performance . The format of the DDR timmings like this. CL-tRCD-tRP-tRAS-CMD. Let see one bye one.

Column Address Strobe(CAS) Latency(CL):

Once the memory controller issue the read command after some clock cycles(delay) it will receive the data in the DQ pins. This delay is called as CAS Latency(CL) This time is expressed in terms of clock cycles.

Example:
1. CL3 means that the memory controller must wait three clock cycles untill the data is delivered after the request is made.
2. CL5 means it must wait five clock cycles.

Diagram.

CAS Latency Functional Diagram

tRCD (RAS to CAS Delay):

By activating the Row&Column we can access the memory cells in the RAM. This activation is done by two control signals Row Address Strobe(RAS) and Column Address Strobe(CAS). If the timing between these two signals is less we can access the data sooner. Here tRCD timing indicates the delay between the Active(Enabling the row/column) and Read/Write Command. tRCD measures this time.

Diagram

tRCD Functional Diagram

tRP(RAS Precharge):

Using the tRCD Signals we activate the particular Row&Column and access the data, after this we need to deactivate the same. RAS Precharge time (tRP) is the time taken between the activate and deactivate the row/column.

tRAS:

After the active command issued its need to wait particualr time for deactivate the row. That time is defined in tRAS.

Command Rate(CMD):

Its the time between selecting the chip and placing the read/write command. This is indicates as T. 1T or 2T 1/2 clock cycles.

Prefetch:

DRAM store the data in the array of capacitors. For single clock pulse the DDR memory transfer 2bits from memory to the memory internal I/O Buffer. This is called as 2-bit prefetch. For DDR2 it increased as 4bit prefetch and DDR3 its 8-Bit Prefetch.

Diagram

n-bit Prefettching

Memory Access:

Using the above timming parameter now we can see how we can access the memory. As we know ram is contain array of  row& column. The capactiy of the individual chips is determine by the no of row and cloumns, when several arrays are combined and they create memory bank.

From the processor we can access the memory by using following control signals.

1. Row Address Strobe (RAS)
2. Column Address Strobe(CAS)
3. Chip Select (CS)
4. Write Enable(WE)
5. Several Commands.

Memory Access Flow

1. The memory controller selects the active row & column by issuing active command for this the controller has wait tRCD clock cycles.
2. Place the Read command.
3. Wait for CL(CAS Latency) no of cycles and get the data in the DQ pins.
4. Once the data recieve the controller wiill deactivate the particualr row, which is done by tRP time.
5. Once the row is active it needs to wait(tRAS cycles) to de-activate the particular row.

Makefile

Makefile is a file which is used for determines which code needs to be recompiled in a large software package. Using the make utility, we can execute the makefile. Makefile contains set of rules and these rules tells how to compile the particular source file.

Rule Syntax:

target : Prerequisite

Actions

Target  : Output file name or action

Example :  hello.o

Action :  Action indicates how to compile the prerequiste and generate the target.

Prerequisite : Input file which is going to generate the target.

Example:

hello.o : hello.c

gcc -c hello.c

default goal:

When giving the make command with out any target like(make). It will start exceute from the first target.

Example:  Makefile

king.o : king.c

gcc -c king.c

slave.o :slave.c

gcc -c slave.c

[simplefundas@localhost make_prog]$ make.

In the command prompt if we give make like this it will first execute the king target and next its start to exceute the slave target. If you want to execute the slave target

first you need to define withe the .DEFAULT_GOAL macro.

Example : Modified Makefile

.DEFAULT_GOAL := slave.o

king.o : king .c:

gcc -c king.c

slave.o : slave.c

gcc -c slave.c

Now It will comiple only slave.o. Because the .DEFAULT_GOAL is pointing slave.o.